1. Field of the Invention
This invention relates to MOSFET semiconductor memory integrated circuits devices and more particularly to improved full Complementary Metal Oxide Semiconductor (CMOS) Static random access memory (SRAM) memory cells.
2. Description of Related Art
Integrated circuit (IC) memory devices are made up of a plurality of memory cells. In general, one basic memory cell design is duplicated numerous times to form those cells. The basic cell design may be modified slightly from cell to cell, for example one cell may be a reversed image or complement of an adjacent cell, but the entire memory device can be described according to the basic cell design.
In the case of Static Random Access Memory (SRAM) devices, the basic cell is usually in one of two forms, either a six transistor (6T) cell or four transistor/two resistor (4T/2R) cell. Many conventional SRAMs using a 6T configuration have six transistors formed in a bulk semiconductor substrate such as single crystal silicon. That type of SRAM is usually embodied in a Complementary Metal Oxide Semiconductor (CMOS) technology, with four transistors being N-channel devices while the remaining two transistors are P-channel devices. A 6T SRAM device operates at relatively low power levels and the bulk transistors have good electrical characteristics, including high mobility and low threshold voltages. Also 6T SRAMs are relatively stable, having high immunity to cell errors, such as those caused by incident alpha particles. However, 6T SRAM cells formed of transistors in a bulk substrate require a large area because the transistors are formed next to one another in the substrate and are essentially in the same plane; which use of six bulk transistors imposes an undesirable lower limit on the cell size. Achieving the smallest cell size with the simplest process reduces the manufacturing costs, increases memory capacity, and increases the device performance without increasing the overall device size.
U.S. Pat. No. 5,394,358 of Huang for "SRAM Memory Cell with Tri-level Local Interconnect" shows a method of forming a 6T SRAM that reduces the number of local interconnections. However, these patents do not show the butted contact structure of the invention.
U.S. Pat. No. 5,330,929 of Pfiester et al. for "Method of Making a Six Transistor Static Random Access Memory Cell" shows a method of making a six transistor (6T) SRAM Cell. However, Pfiester et al. does not show the butted contact of this invention, but does include an SRAM cell and a method of forming a memory cell, wherein the memory cell may comprise an active region and a first layer. The active region include first, second and third segments. The first segment has an adjacent end and a distal end. The second segment, generally parallel to the first segment, has an adjacent end and a distal end. For the third segment, generally perpendicular to the first direction, the adjacent end of the first segment lies near an end of the third segment. The adjacent end of the second segment lies near the other end of the third segment. The first layer is shaped similarly to the active region except that the first layer does not lie over the first and second segments near the distal ends. This invention includes an SRAM cell and a method of forming the memory cell, wherein the memory cell comprises shared gate gate electrodes that overlap one another without electrically contacting each other.